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Design Verification Engineer (GPU) - San Jose, CA

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Design Verification Engineer (GPU) - San Jose, CA

  • Location:

    San Jose

  • Sector:

    ConSol US Information Technology

  • Job type:

    Temporary & Contract

  • Salary:

    US$80.00 - US$120.00 per hour + Insurances

  • Contact:

    Amy Joyner

  • Contact email:

  • Job ref:


  • Published:

    about 2 months ago

  • Expiry date:


  • Client:

    ConSol Partners

The Company

Our client is a global leader in technology and has been transforming the electronics we use every day - TVs, smartphones, wearable devices, tablets, etc. Since being established, our client has grown into a global brand and is now one of the leading technology companies in the world and a reputable, globally recognized brand.

The Role

As a GPU Design Verification Engineer, your talents will ensure the quality of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date IEEE UVM version will place you among the elite within our profession.

The Individual:

As the ideal candidate you will have the following skill and experience:

  • Development & debugging
  • Knowledge of Block-level (unit level)
  • UVM, SystemVerilog
  • Work with architects and designers to build verification environments and test plans
  • Create verification coverage strategy to ensure complete test suite implementation
  • Develop assertions and checks to optimize isolation time and produce meaningful failing signatures
  • Analyze failing tests to root cause along, working with RTL and reference modelling teams
  • Examine code coverage results, identifying exclusions and improving stimulus

Minimum requirements:

  • BS in Computer Engineering, BSEE or comparable and 8 years of industry experience in a design verification role
  • Proficient in System Verilog/UVM/OVM, and OOP/C++
  • Deep understanding of constrained randomization and the development of efficient test suites
  • Experience with code coverage and functional coverage-driven verification methodology.
  • Experience in creating, running and debugging of SystemVerilog/UVM constraint-random testbench.
  • Working knowledge of scripting languages such as Python or Perl
  • Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines Preferred qualifications:
  • Good verbal and written communication skills
  • Experience of GPU or CPU is a plus


Location: Austin, TX (The role is hybrid and will be onsite 3x per week)

Salary: $80-$100/hour on a W2 basis

Contact Details:

ConSol Partners

We are a leading consultancy for expansion in communications, content and emerging technology markets. We work in collaboration with growing organizations on exclusive assignments to find them the best talent in the industry.