Our client is a global leader in technology and has been transforming the electronics we use every day - TVs, smartphones, wearable devices, tablets, etc. Since being established, our client has grown into a global brand and is now one of the leading technology companies in the world and a reputable, globally recognized brand.
As a Senior Designer on coherent interconnect micro-architect, you will be responsible for working on the micro-architecture development of custom coherent interconnect IP and/or last level cache blocks. In this role you will be interacting with the system architects, verification, performance/power and design implementation teams. You will be owning and driving the critical coherent interconnect related RTL design, performance and power optimization and also work on logic debug and timing closure of the design.
As the ideal candidate you will have the following skill and experience:
- Experience in development and debugging of new features on coherent interconnect IP and/or cache level (LLC) blocks.
- Previous experience owning and driving RTL design
- Previous experience working on LINT, ECO and CDC flows and analysis
- Previous experience working on SOC IP delivery
- Knowledge of power artist flow and power analysis
APPLY NOW - INTERVIEWING IMMEDIATELY
Location: Austin, TX (The role is hybrid and will be onsite 3x per week)
Rate: Up to $95/hour DOE on a W2 basis
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